M-PSK Demodulator With Joint Carrier and Timing Recovery

In this brief, we propose a new digital receiver for Phase-Shift Keying (PSK) modulation based on the integration of conventional Costas Loop circuit with timing recovery method. The is applied to PSK demodulator using an Iterative Learning Control (ILC) law and it minimization intersymbol interference only one sample per symbol. main advantage proposed method insensitivity frequency offsets which results in improved performance robustness circuit. Experiments comparing (cascade Early-Late Timing Synchronizer) scenarios characterized by low signal-to-noise ratios large phase errors, show that time needed reduce errors seven times smaller than receiver. Moreover, impact necessary hardware resources (area power consumption) negligible.